Rigel Instruction Timing The execution time of an instruction depends on the instruction itself, the addressing modes of the instruction specifiers, and the special cases invoked by the instruction (cache miss, TB miss, unaligned operand, etc). In the most general case, the instruction execution time is the sum of the specifier times and the execute, fetch time. inst time = spec 1 time +...+ spec n time + execute, fetch time All times are given in microcycles and I/O cycles. A number 'n' represents n microcycles; 'n'R represents n read cycles; and 'n'W represents n write cycles. Read cycles that hit in the cache take 1 microcycle; read cycles that miss in the cache take at least 2 extra cycles, depending on the speed of external memory. Write cycles always take one cycle, unless the external interface is busy. 1 Specifier Timing The first table covers all specifiers except the last; the second and third tables cover the last specifier; the last table covers stall time due to specifier interaction. Specifier addressing modes are cross-indexed with specifier access type: r = read a = address v = field m = modify w = write and data length: b = byte w = word l = long or f_floating q = quadword or d_floating or g_floating. Branch displacements are NOT considered to be specifiers; handling of branch displacements is included in the execute, fetch timing tables. 1.1 Specifier Timing (Not The Last Specifier) Only access types a, v, and r occur in these specifiers. addressing mode | r.bwl av.bwl r.q av.q ---------------------------+-------------------------------- not indexed: | short literal #n | 1 - 2 - register Rn | 1 2 2 2 register def (Rn) | 1r 1 2r 1 autodecrement -(Rn) | 1+1r 2 1+2r 2 autoincrement (Rn)+ | 1+1r 2 1+2r 2 immediate i^#n | 1 1 3+1r 1 autoinc def @(Rn)+ | 1+2r 1+1r 1+3r 1+1r absolute @#a | 1r 1 2r 1 displ/relative d(Rn) | 1r 1 2r 1 displ/rel def @d(Rn) | 1+2r 1r 1+3r 1r indexed: | short literal | - - - - register | - - - - register def (Rn)[Rx] | 1+1r 2 1+2r 2 autodecrement -(Rn)[Rx] | 2+1r 3 2+2r 3 autoincrement (Rn)+[Rx] | 2+1r 3 2+2r 3 immediate | - - - - autoinc def @(Rn)+[Rx] | 2+2r 3+1r 2+3r 3+1r absolute @#a[Rx] | 1+1r 2 1+2r 2 displ/relative d(Rn)[Rx] | 2+1r 3 2+2r 3 displ/rel def @d(Rn)[Rx] | 2+2r 3+1r 2+3r 3+1r 1.2 Specifier Timing (Last Specifier) Access types a, v, r, m, and w are permitted in the last specifier. This table covers data lengths byte, word, and long. addressing mode | r.bwl av.bwl m.bwl w.bwl ---------------------------+-------------------------------- not indexed: | short literal #n | 1 - - - register Rn | 0 0 1 0 note 1 register def (Rn) | 1r 1 1r+1w 1w autodecrement -(Rn) | 1+1r 2 1+1r+1w 1+1w autoincrement (Rn)+ | 1+1r 2 1+1r+1w 1+1w immediate i^#n | 1 1 - - autoinc def @(Rn)+ | 1+2r 1+1r 1+2r+1w 1+1r+1w absolute @#a | 1r 1 1r+1w 1w displ/relative d(Rn) | 1r 1 1r+1w 1w displ/rel def @d(Rn) | 1+2r 1r 1+2r+1w 1+1r+1w indexed: | short literal | - - - - register | - - - - register def (Rn)[Rx] | 1+1r 2 1+1r+1w 1+1w autodecrement -(Rn)[Rx] | 2+1r 3 2+1r+1w 2+1w autoincrement (Rn)+[Rx] | 2+1r 3 2+1r+1w 2+1w immediate | - - - - autoinc def @(Rn)+[Rx] | 2+2r 3+1r 2+2r+1w 2+1r+1w absolute @#a[Rx] | 1+1r 2 1+1r+1w 1+1w displ/relative d(Rn)[Rx] | 2+1r 3 2+1r+1w 2+1w displ/rel def @d(Rn)[Rx] | 2+2r 3+1r 2+2r+1w 2+1r+1w Note 1: If the last specifier is the only specifier, all register mode specifiers take one cycle. This table covers data length quad. Note that back to back writes stall for two cycles; this is already included in the modify and write columns. addressing mode | r.q av.q m.q w.q ---------------------------+-------------------------------- not indexed: | short literal #n | 2 - - - register Rn | 0 0 2 1 note 2 register def (Rn) | 2r 1 2+2r+2w 2+2w autodecrement -(Rn) | 1+2r 2 3+2r+2w 3+2w autoincrement (Rn)+ | 1+2r 2 3+2r+2w 3+2w immediate i^#n | 4 4 - - autoinc def @(Rn)+ | 1+3r 1+1r 3+3r+2w 3+1r+2w absolute @#a | 2r 1 2+2r+2w 2+2w displ/relative d(Rn) | 2r 1 2+2r+2w 2+2w displ/rel def @d(Rn) | 1+3r 1r 3+3r+2w 3+1r+2w indexed: | short literal | - - - - register | - - - - register def (Rn)[Rx] | 1+2r 2 3+2r+2w 3+2w autodecrement -(Rn)[Rx] | 2+2r 3 4+2r+2w 4+2w autoincrement (Rn)+[Rx] | 2+2r 3 4+2r+2w 4+2w immediate | - - - - autoinc def @(Rn)+[Rx] | 2+3r 3+1r 4+3r+2w 4+1r+2w absolute @#a[Rx] | 1+2r 2 3+2r+2w 3+2w displ/relative d(Rn)[Rx] | 2+2r 3 4+2r+2w 4+2w displ/rel def @d(Rn)[Rx] | 2+3r 3+1r 4+3r+2w 4+1r+2w Note 2: If the last specifier is the only specifier, all register mode specifiers take two cycles. 1.3 Specifier Stall Timing Specifier stall occurs in the following circumstances: o Second to last specifier accesses memory, access mode read or modify; last specifier is register (eg, ADDL2 d(r),r). o Last specifier accesses memory, access mode read or modify (eg, ADDL2 r,d(r)). Specifier stall is always one cycle. 2 Execute, Fetch Timing The execute, fetch timing covers the execution time of the current instruction and the normally buried prefetch time for the next instruction. If the current instruction is a branch, the fetch time of the next instruction cannot be buried and is accounted for in this table. The standard notation for operand specifiers is: . where: o Name is a suggestive name for the operand in the context of the instruction. It is the capitalized name of a register or block for implied operands. o Access type is a letter denoting the operand specifier access type. a = address operand b = branch displacement m = modified operand (both read and written) r = read only operand v = field operand w = write only operand o Data type is a letter denoting the data type of the operand. b = byte d = d_floating f = f_floating g = g_floating l = longword q = quadword v = field (used only in implied operands) w = word * = multiple longwords (used only in implied operands) o Implied operands, that is, locations that are accessed by the instruction, but not specified in an operand, are denoted by curly braces {}. 2.1 Integer Arithmetic and Logical Instructions Opcode Instruction Execution Cycles ------ ----------- ---------------- 58 ADAWI add.rw, sum.mw 0 sum = reg 4 sum = mem 80 ADDB2 add.rb, sum.mb 0 C0 ADDL2 add.rl, sum.ml 0 A0 ADDW2 add.rw, sum.mw 0 81 ADDB3 add1.rb, add2.rb, sum.wb 1 C1 ADDL3 add1.rl, add2.rl, sum.wl 1 A1 ADDW3 add1.rw, add2.rw, sum.ww 1 D8 ADWC add.rl, sum.ml 1 78 ASHL cnt.rb, src.rl, dst.wl 6-8, 8 typ 79 ASHQ cnt.rb, src.rq, dst.wq 7-10, 9 typ 8A BICB2 mask.rb, dst.mb 0 CA BICL2 mask.rl, dst.ml 0 AA BICW2 mask.rw, dst.mw 0 8B BICB3 mask.rb, src.rb, dst.wb 1 CB BICL3 mask.rl, src.rl, dst.wl 1 AB BICW3 mask.rw, src.rw, dst.ww 1 88 BISB2 mask.rb, dst.mb 0 C8 BISL2 mask.rl, dst.ml 0 A8 BISW2 mask.rw, dst.mw 0 89 BISB3 mask.rb, src.rb, dst.wb 1 C9 BISL3 mask.rl, src.rl, dst.wl 1 A9 BISW3 mask.rw, src.rw, dst.ww 1 93 BITB mask.rb, src.rb 1 D3 BITL mask.rl, src.rl 1 B3 BITW mask.rw, src.rw 1 94 CLRB dst.wb 1 D4 CLRL{=F} dst.wl 1 7C CLRQ{=D=G} dst.wq 1 B4 CLRW dst.ww 1 91 CMPB src1.rb, src2.rb 1 D1 CMPL src1.rl, src2.rl 1 B1 CMPW src1.rw, src2.rw 1 98 CVTBL src.rb, dst.wl 2 dst = reg 3 dst = mem 99 CVTBW src.rb, dst.wl 3 F6 CVTLB src.rl, dst.wb 4 F7 CVTLW src.rl, dst.ww 4 33 CVTWB src.rw, dst.wb 4 32 CVTWL src.rw, dst.wl 2 dst = reg dst = mem 97 DECB dif.mb 1 D7 DECL dif.ml 1 B7 DECW dif.mw 1 86 DIVB2 divr.rb, quo.mb 17-21, 18 typ C6 DIVL2 divr.rl, quo.ml 41-45, 42 typ A6 DIVW2 divr.rw, quo.mw 25-29, 26 typ 87 DIVB3 divr.rb, divd.rb, quo.wb 18-22, 19 typ C7 DIVL3 divr.rl, divd.rl, quo.wl 42-46, 43 typ A7 DIVW3 divr.rw, divd.rw, quo.ww 26-30, 27 typ 7B EDIV divr.rl, divd.rq, quo.vl, rem.wl 44-46, 44 typ 7A EMUL mulr.rl, muld.rl, add.rl, prod.wq 38 96 INCB sum.mb 1 D6 INCL sum.ml 1 B6 INCW sum.mw 1 92 MCOMB src.rb, dst.wb 1 D2 MCOML src.rl, dst.wl 1 B2 MCOMW src.rw, dst.ww 1 8E MNEGB src.rb, dst.wb 1 CE MNEGL src.rl, dst.wl 1 AE MNEGW src.rw, dst.ww 1 90 MOVB src.rb, dst.wb 1 D0 MOVL src.rl, dst.wl 1 7D MOVQ src.rq, dst.wq 1 B0 MOVW src.rw, dst.ww 1 9A MOVZBW src.rb, dst.wb 1 9B MOVZBL src.rb, dst.wl 1 3C MOVZWL src.rw, dst.ww 1 84 MULB2 mulr.rb, prod.mb 16 C4 MULL2 mulr.rl, prod.ml 37 w/o FPA tbd with FPA A4 MULW2 mulr.rw, prod.mw 24 85 MULB3 mulr.rb, muld.rb, prod.wb 17 C5 MULL3 mulr.rl, muld.rl, prod.wl 38 w/o FPA tbd with FPA A5 MULW3 mulr.rw, muld.rw, prod.ww 25 DD PUSHL src.rl, {-(SP).wl} 2+1w 9C ROTL cnt.rb, src.rl, dst.wl 4 D9 SBWC sub.rl, dif.ml 1 82 SUBB2 sub.rb, dif.mb 0 C2 SUBL2 sub.rl, dif.ml 0 A2 SUBW2 sub.rw, dif.mw 0 83 SUBB3 sub.rb, min.rb, dif.wb 1 C3 SUBL3 sub.rl, min.rl, dif.wl 1 A3 SUBW3 sub.rw, min.rw, dif.ww 1 95 TSTB src.rb 1 D5 TSTL src.rl 1 B5 TSTW src.rw 1 8C XORB2 mask.rb, dst.mb 0 CC XORL2 mask.rl, dst.ml 0 AC XORW2 mask.rw, dst.mw 0 8D XORB3 mask.rb, src.rb, dst.wb 1 CD XORL3 mask.rl, src.rl, dst.wl 1 AD XORW3 mask.rw, src.rw, dst.ww 1 2.2 Address Instructions Opcode Instruction Execution Cycles ------ ----------- ---------------- 9E MOVAB src.ab, dst.wl 1 DE MOVAL{=F} src.al, dst.wl 1 7E MOVAQ{=D=G} src.aq, dst.wl 1 3E MOVAW src.aw, dst.wl 1 9F PUSHAB src.ab, {-(SP).wl} 2+1w DF PUSHAL{=F} src.al, {-(SP).wl} 2+1w 7F PUSHAQ{=D=G} src.aq, {-(SP).wl} 2+1w 3F PUSHAW src.aw, {-(SP).wl} 2+1w 2.3 Variable Length Bit Field Instructions Opcode Instruction Execution Cycles ------ ----------- ---------------- EC CMPV pos.rl, size.rb, base.vb, 9 v = reg {field.rv}, src.rl 13+1r - 13+2r, 13+1r typ v = mem ED CMPZV pos.rl, size.rb, base.vb, 9 v = reg {field.rv}, src.rl 13+1r - 13+2r, 13+1r typ v = mem EE EXTV pos.rl, size.rb, base.vb, 9 v = reg {field.rv}, dst.wl 13+1r - 13+2r, 13+1r typ v = mem EF EXTZV pos.rl, size.rb, base.vb, 9 v = reg {field.rv}, dst.wl 13+1r - 13+2r, 13+1r typ v = mem F0 INSV src.rl, pos.rl, size.rb, base.vb, 10-11, 10 typ v = reg {field.wv} 14+1r+1w - 14+2r+2w, 14+1r+1w typ v = mem EB FFC startpos.rl, size.rb, base.vb, 15-24, 19 typ v = reg {field.rv}, findpos.wl 19+1r - 28+2r, 23+1r typ v = mem EA FFS startpos.rl, size.rb, base.vb, 14-24, 18 typ v = reg {field.rv}, findpos.wl 18+1r - 27+2r, 22+1r typ v = mem 2.4 Control Instructions The number before the slash is cycles for branch not taken, after the slash for branch taken. If the opcode and first specifier of the instruction at the branch target of a taken branch overlap a longword boundary, add 1r cycle to the branch taken execution time. Opcode Instruction Execution Cycles ------ ----------- ---------------- 9D ACBB limit.rb, add.rb, index.mb, displ.bw 10+2r/8+1r F1 ACBL limit.rl, add.rl, index.ml, displ.bw 10+2r/8+1r 3D ACBW limit.rw, add.rw, index.mw, displ.bw 10+2r/8+1r F3 AOBLEQ limit.rl, index.ml, displ.bb 7+2r/4+1r i = reg 10+2r/7+1r i = mem F2 AOBLSS limit.rl, index.ml, displ.bb 7+2r/4+1r i = reg 10+2r/7+1r i = mem 1E BCC{=BGEQU} displ.bb 1/4+1r 1F BCS{=BLSSU} displ.bb 1/4+1r 13 BEQL{=BEQLU} displ.bb 1/4+1r 18 BGEQ displ.bb 1/4+1r 14 BGTR displ.bb 1/4+1r 1A BGTRU displ.bb 1/4+1r 15 BLEQ displ.bb 1/4+1r 1B BLEQU displ.bb 1/4+1r 19 BLSS displ.bb 1/4+1r 12 BNEQ{=BNEQU} displ.bb 1/4+1r 1C BVC displ.bb 1/4+1r 1D BVS displ.bb 1/4+1r E1 BBC pos.rl, base.vb, displ.bb, {field.rv} 5/8+1r v = reg 7+1r/10+2r v = mem E0 BBS pos.rl, base.vb, displ.bb, {field.rv} 5/8+1r v = reg 7+1r/10+2r v = mem E5 BBCC pos.rl, base.vb, displ.bb, {field.mv} 6/9+1r v = reg 7+1r+1w/10+2r+1w v = mem E3 BBCS pos.rl, base.vb, displ.bb, {field.mv} 6/9+1r v = reg 7+1r+1w/10+2r+1w v = mem E4 BBSC pos.rl, base.vb, displ.bb, {field.mv} 6/9+1r v = reg 7+1r+1w/10+2r+1w v = mem E2 BBSS pos.rl, base.vb, displ.bb, {field.mv} 6/9+1r v = reg 7+1r+1w/10+2r+1w v = mem E7 BBCCI pos.rl, base.vb, displ.bb, {field.mv} 6/9+1r v = reg 7+1r+1w/10+2r+1w v = mem E6 BBSSI pos.rl, base.vb, displ.bb, {field.mv} 6/9+1r v = reg 7+1r+1w/10+2r+1w v = mem E9 BLBC src.rl, displ.bb 2/5+1r E8 BLBS src.rl, displ.bb 2/5+1r 11 BRB displ.bb 4+1r 31 BRW displ.bw 4+1r 10 BSBB displ.bb, {-(SP).wl} 4+1r+1w 30 BSBW displ.bw, {-(SP).wl} 4+1r+1w 8F CASEB selector.rb, base.rb, limit.rb, 12+2r/9+1r displ.bw-list CF CASEL selector.rl, base.rl, limit.rl, 12+2r/9+1r displ.bw-list AF CASEW selector.rw, base.rw, limit.rw, 12+2r/9+1r displ.bw-list 17 JMP dst.ab 4+1r 16 JSB dst.ab, {-(SP).wl} 4+1r+1w 05 RSB {(SP)+.rl} 5+2r F4 SOBGEQ index.ml, displ.bb 6+2r/4+1r i = reg 9+2r/6+1r i = mem F5 SOBGTR index.ml, displ.bb 6+2r/4+1r i = reg 9+2r/6+1r i = mem 2.5 Procedure Call Instructions In this section, n = number of set register bits in the procedure call mask. The register writes in CALLx are done with 64b (packed) writes; if there are more than 4 registers to be pushed, stalls will result. Opcode Instruction Execution Cycles ------ ----------- ---------------- FA CALLG arglist.ab, dst.ab, {-(SP).w*} 16+2r+5w+max(3,nw) FB CALLS numarg.rl, dst.ab, {-(SP).w*} 16+2r+6w+max(3,nw) 04 RET {(SP)+.r*} 14+5r+max(4,n+nr) G 15+5r+max(4,n+nr) S 2.6 Miscellaneous Instructions In this section, n = number of set register bits in the register mask. If more than 4 registers are pushed in PUSHR, stalls will result. Opcode Instruction Execution Cycles ------ ----------- ---------------- B9 BICPSW mask.rw 8 B8 BISPSW mask.rw 8 03 BPT {-(KSP).w*} exception 00 HALT {-(KSP).w*} 2 0A INDEX subscript.rl, low.rl, high.rl, 7 size = 1 size.rl, indexin.rl, indexout.wl 40 size <> 1 DC MOVPSL dst.wl 2 01 NOP 1 BA POPR mask.rw, {(SP)+.r*} 13+1r+max(4,n+nr) BB PUSHR mask.rw, {-(SP).w*} 14+max(3,nw) FC XFC {unspecified operands} exception 2.7 Queue Instructions Opcode Instruction Execution Cycles ------ ----------- ---------------- 5C INSQHI entry.ab, header.aq 14+3r+5w 5D INSQTI entry.ab, header.aq 18+3r+6w 0E INSQUE entry.ab, pred.ab 5+1r+5w 5E REMQHI header.aq, addr.wl 17+3r+3w 5F REMQTI header.aq, addr.wl 21+4r+4w 0F REMQUE entry.ab, addr.wl 6+2r+2w 2.8 Character String Instructions For CMPC3, CMPC5, LOCC, SKPC, SCANC, SPANC, n = characters processed in main loop; k = characters processed in fill loop. For MOVC3, MOVC5, n = LONGWORDS processed in main loop; k = LONGWORDS processed in fill loop. Opcode Instruction Execution Cycles ------ ----------- ---------------- 29 CMPC3 len.rw, src1addr.ab, src2addr.ab 5+7n+2nr 2D CMPC5 src1len.rw, src1addr.ab, fill.rb, 5+7n+2nr+6k+kr src2len.rw, src2addr.ab 3A LOCC char.rb, len.rw, addr.ab 4+6n+nr 28 MOVC3 len.rw, srcaddr.ab, dstaddr.ab 19+2n+nr+nw 2C MOVC5 srclen.rw, srcaddr.ab, fill.rb, 34+2n+nr+nw+3k+kw dstlen.rw, dstaddr.ab 2A SCANC len.rw, addr.ab, tbladdr.ab, mask.rb 5+7n+2nr 3B SKPC char.rb, len.rw, addr.ab 4+6n+nr 2B SPANC len.rw, addr.ab, tbladdr.ab, mask.rb 5+7n+2nr 2.9 Operating System Support Instructions The writes in SVPCTX are done with 64b packed writes; memory stalls may result. Opcode Instruction Execution Cycles ------ ----------- ---------------- BD CHME param.rw, {-(ySP).w*} 21+2r+3w BC CHMK param.rw, {-(ySP).w*} 21+2r+3w BE CHMS param.rw, {-(ySP).w*} 21+2r+3w BF CHMU param.rw, {-(ySP).w*} 21+2r+3w Where y=MINU(x, PSL) 06 LDPCTX {PCB.r*, -(KSP).w*} 32+24r+2w DB MFPR procreg.rl, dst.wl 8-15, 13 typ DA MTPR src.rl, procreg.rl 11-15, 13 typ 0C PROBER mode.rb, len.rw, base.ab 16-19, 16 typ 0D PROBEW mode.rb, len.rw, base.ab 16-19, 16 typ 02 REI {(SP)+.r*} 18+3r - 21+3r, 19+3r typ 07 SVPCTX {(SP)+.r*, PCB.w*} 6+2r+20w - 9+2r+20w, 9+2r+20w typ 2.10 Floating Point Instructions Opcode Instruction Execution Cycles ------ ----------- ---------------- 60 ADDD2 add.rd, sum.md tbd 40 ADDF2 add.rf, sum.mf tbd 40FD ADDG2 add.rg, sum.mg tbd 61 ADDD3 add1.rd, add2.rd, sum.wd tbd 41 ADDF3 add1.rf, add2.rf, sum.wf tbd 41FD ADDG3 add1.rg, add2.rg, sum.wg tbd 71 CMPD src1.rd, src2.rd tbd 51 CMPF src1.rf, src2.rf tbd 51FD CMPG src1.rg, src2.rg tbd 6C CVTBD src.rb, dst.wd tbd 4C CVTBF src.rb, dst.wf tbd 4CFD CVTBG src.rb, dst.wg tbd 68 CVTDB src.rd, dst.wb tbd 76 CVTDF src.rd, dst.wf tbd 6A CVTDL src.rd, dst.wl tbd 69 CVTDW src.rd, dst.ww tbd 48 CVTFB src.rf, dst.wb tbd 56 CVTFD src.rf, dst.wd tbd 99FD CVTFG src.rf, dst.wg tbd 4A CVTFL src.rf, dst.wl tbd 49 CVTFW src.rf, dst.ww tbd 48FD CVTGB src.rg, dst.wb tbd 33FD CVTGF src.rg, dst.wf tbd 4AFD CVTGL src.rg, dst.wl tbd 49FD CVTGW src.rg, dst.ww tbd 6E CVTLD src.rl, dst.wd tbd 4E CVTLF src.rl, dst.wf tbd 4EFD CVTLG src.rl, dst.wg tbd 6D CVTWD src.rw, dst.wd tbd 4D CVTWF src.rw, dst.wf tbd 4DFD CVTWG src.rw, dst.wg tbd 6B CVTRDL src.rd, dst.wl tbd 4B CVTRFL src.rf, dst.wl tbd 4BFD CVTRGL src.rg, dst.wl tbd 66 DIVD2 divr.rd, quo.md tbd 46 DIVF2 divr.rf, quo.mf tbd 46FD DIVG2 divr.rg, quo.mg tbd 67 DIVD3 divr.rd, divd.rd, quo.wd tbd 47 DIVF3 divr.rf, divd.rf, quo.wf tbd 47FD DIVG3 divr.rg, divd.rg, quo.wg tbd 72 MNEGD src.rd, dst.wd tbd 72 MNEGD src.rd, dst.wd tbd 52FD MNEGG src.rg, dst.wg tbd 70 MOVD src.rd, dst.wd tbd 50 MOVF src.rf, dst.wf tbd 50FD MOVG src.rg, dst.wg tbd 64 MULD2 mulr.rd, prod.md tbd 44 MULF2 mulr.rf, prod.mf tbd 44FD MULG2 mulr.rg, prod.mg tbd 65 MULD3 mulr.rd, muld.rd, prod.wd tbd 45 MULF3 mulr.rf, muld.rf, prod.wf tbd 45FD MULG3 mulr.rg, muld.rg, prod.wg tbd 62 SUBD2 sub.rd, dif.md tbd 42 SUBF2 sub.rf, dif.mf tbd 42FD SUBG2 sub.rg, dif.mg tbd 63 SUBD3 sub.rd, min.rd, dif.wd tbd 43 SUBF3 sub.rf, min.rf, dif.wf tbd 43FD SUBG3 sub.rg, min.rg, dif.wg tbd 73 TSTD src.rd tbd 53 TSTF src.rf tbd 53FD TSTG src.rg tbd 2.11 Microcode-Assisted Emulated Instructions The times gives here are for execution of the emulation exception. Opcode Instruction Execution Cycles ------ ----------- ---------------- 20 ADDP4 addlen.rw, addaddr.ab, sumlen.rw, 18+2r+10w sumaddr.ab 21 ADDP6 add1len.rw, add1addr.ab, add2len.rw, 18+2r+10w add2addr.ab, sumlen.rw, sumaddr.ab F8 ASHP cnt.rb, srclen.rw, srcaddr.ab, round.rb, 18+2r+10w dstlen.rw, dstaddr.ab 35 CMPP3 len.rw, src1addr.ab, src2addr.ab 18+2r+10w 37 CMPP4 src1len.rw, src1addr.ab, src2len.rw, 18+2r+10w src2addr.ab 0B CRC tbl.ab, inicrc.rl, strlen.rw, stream.ab 18+2r+10w F9 CVTLP src.rl, dstlen.rw, dstaddr.ab 18+2r+10w 36 CVTPL srclen.rw, srcaddr.ab, dst.wl 18+2r+10w 08 CVTPS srclen.rw, srcaddr.ab, dstlen.rw, 18+2r+10w dstaddr.ab 09 CVTSP srclen.rw, srcaddr.ab, dstlen.rw, 18+2r+10w dstaddr.ab 24 CVTPT srclen.rw, srcaddr.ab, tbladdr.ab, 18+2r+10w dstlen.rw, dstaddr.ab 26 CVTTP srclen.rw, srcaddr.ab, tbladdr.ab, 18+2r+10w dstlen.rw, dstaddr.ab 27 DIVP divrlen.rw, divraddr.ab, divdlen.rw, 18+2r+10w divdaddr.ab, quolen.rw, quoaddr.ab 38 EDITPC srclen.rw, srcaddr.ab, pattern.ab, 18+2r+10w dstaddr.ab 39 MATCHC objlen.rw, objaddr.ab, srclen.rw, 18+2r+10w srcaddr.ab 34 MOVP len.rw, srcaddr.ab, dstaddr.ab 18+2r+10w 2E MOVTC srclen.rw, srcaddr.ab, fill.rb, 18+2r+10w tbladdr.ab, dstlen.rw, dstaddr.ab 2F MOVTUC srclen.rw, srcaddr.ab, esc.rb, 18+2r+10w tbladdr.ab, dstlen.rw, dstaddr.ab 25 MULP mulrlen.rw, mulraddr.ab, muldlen.rw, 18+2r+10w muldaddr.ab, prodlen.rw, prodaddr.ab 22 SUBP4 sublen.rw, subaddr.ab, diflen.rw, 18+2r+10w difaddr.ab 23 SUBP6 sublen.rw, subaddr.ab, minlen.rw, 18+2r+10w minaddr.ab, diflen.rw, difaddr.ab 2.12 Other Timings Event Execution Cycles ------ ---------------- initiate hardware interrupt 22+3r+2w initiate software interrupt 21+2r+2w initiate exception 28+2r+2w - 50+2r+8w, 35+2r+3w typ unaligned read operand (word or longword) 1r unaligned read operand (quadword) 2r unaligned write operand (word or longword) 2+1w unaligned write operand (quadword) 4+2w TB read miss, system space 7+1r TB write miss, system space, m bit set 11+1r TB write miss, system space, m bit clear 15+1r+1w TB read miss, process space, single miss 10+1r TB write miss, process space, single miss, m bit set 13+1r TB write miss, process space, single miss, m bit clear 17+1r+1w TB read miss, process space, double miss 17+2r TB write miss, process space, double miss, m bit set 19+2r TB write miss, process space, double miss, m bit clear 23+2r+1w I stream fetch delay after TB miss 5+1r M bit clear, system space 9+2r+1w M bit clear, process space, single miss 9+2r+1w M bit clear, process space, double miss 17+3r+1w Read/write crossing page boundary 7 DMA latency 3 interrupt latency tbd 3 Examples ADDL2 d(r),r - aligned memory operand, cache hit, no TB miss specifier 1 time 1+1r specifier 2 time 1 execute, fetch time 0 ---- total 2+1r MOVL r,d(r) - aligned memory operand, cache hit, no TB miss specifier 1 time 1 specifier 2 time 1+1w execute, fetch time 0 ---- total 2+1w SOBGTR r,disp - cache hit, no TB miss, instruction at branch target spans a longword boundary specifier 1 time 1 (note - 1 specifier) execute, fetch time 4+1r (note - branch taken) unaligned new instruction 1r ---- total 5+2r INDEX d(r),@d(r),(r)[rx],@(r)+,-(r),@d(r)[rx] - all memory operands unaligned across page boundaries, all memory operands take TB misses on both reads, m bit clear, cache hits specifier 1 time 1r specifier 1 cross page 7 specifier 1 TB miss x 2 20+2r specifier 1 unaligned 1r specifier 2 time 1+2r specifier 2 cross page x 2 14 specifier 2 TB miss x 4 40+4r specifier 2 unaligned x 2 2r specifier 3 time 1+1r specifier 3 cross page 7 specifier 3 TB miss x 2 20+2r specifier 3 unaligned 1r specifier 4 time 1+2r specifier 4 cross page x 2 14 specifier 4 TB miss x 4 40+4r specifier 4 unaligned x 2 2r specifier 5 time 1+1r specifier 5 cross page 7 specifier 5 TB miss x 2 20+2r specifier 5 unaligned 1r specifier 6 time 2+1r+1w specifier 6 read cross page 7 specifier 6 write cross page 7 specifier 6 TB miss x 2 20+2r specifier 6 M bit clear x 2 34+2r+2w specifier 6 read unaligned 1r specifier 6 write unaligned 2+1w execute, fetch time 40 ---- total 303+36r+4w